Silicon for Physical AI
Design the silicon that runs Physical AI, from a single NAND gate to an edge-AI accelerator, then out to a real chip. Logic, synthesis, timing, quantization, AI-assisted design, and the economics of getting made, with TinyTapeout as the real-fab capstone.
▶ Start the course ← All coursesWhere this sits, and what moves it.
Binding constraint · The critical path, and the economics of the mask set. Timing decides what a chip can do; the mask decides whether it is ever made.
Designing silicon meant a company. A student could learn the theory and never see a fabricated part, so the loop from a logic decision to a physical die never closed.
Open tooling and a shared shuttle close it, and this course ends at a real fab. AI writing RTL is arriving fast, and the course puts the weight where it belongs: verification is the bottleneck, and a generated design you cannot check is a liability rather than a speedup.
The interesting question is not whether AI writes more RTL -- it will -- but whether the checking scales with it. Watch formal coverage per engineer-hour. If that curve does not bend, generated hardware slows the field down, and if it does, a student with a shuttle slot can do something that used to need a fab.
Every hard thing was impossible until the constraint that made it impossible was named. How we read a frontier →
Logic From One Gate
Build every logic function from a single universal gate, then compose those gates into an adder, the ground floor every chip stands on.
- L1The Universal GateHow many DIFFERENT kinds of logic gate do you need to build any digital circuit, an entire CPU?Build AND, OR, and NOT using only NAND, proving one gate is enough to compute anything.→
- L2The AdderYou chain full adders into an 8-bit ripple-carry adder and the sums come out wrong. Which expression do you check first?Compose gates into a full adder, then chain them into an 8-bit ripple-carry adder that actually adds.→
- L2Write It in VerilogYou write an adder in Verilog and the result truncates. What does declaring the output wide enough do?Write a real adder in Verilog and synthesize it with the actual Yosys, then watch it pass on the synthesized netlist.→
Synthesis & The Cost of Logic
See what a synthesis tool actually does, shrink logic to fewer gates, and why timing (the critical path) decides how fast a chip can run.
- L2Synthesize: Fewer GatesA synthesizer turns your Verilog into a gate netlist. Writing the SAME logic a different way in Verilog usually gives…Take a function written as a raw sum of every true row and factor it into far fewer gates, what logic synthesis (Yosys) does for a living.→
- L3The Critical PathAn 8-bit ripple-carry adder gives the right answer. What sets the fastest clock it can run at?Compute a design's critical-path delay and see why a ripple-carry adder can't hit a fast clock, the timing half of PPA.→
The Edge-AI Accelerator
Build the compute at the heart of every AI chip, the multiply-accumulate array, then quantize it to int8, the trick that makes inference fit on a Physical-AI device.
- L3The MAC ArrayA multiply-accumulate array performs a matrix multiply. What is it counting?Build a multiply-accumulate array that performs a matrix multiply, and count the MACs, the fundamental work of a neural accelerator.→
- L4Quantize for the EdgeYou replace 32-bit float weights and inputs with 8-bit integers and do the matmul in integer MACs. What happens to accuracy?Quantize a float matmul to int8 and show the accuracy holds, the move that lets Physical-AI inference run in a fraction of the power and memory.→
- L4What a learner has to holdAn agent that learns on a microcontroller keeps its network, an eligibility trace, an optimizer statistic and an input normaliser. Roughly what share of its persistent memory is the network's own weights?Build the memory ledger of an agent that learns on a 512 KB microcontroller, recover its numeric precision from the paper's own rounded total, and find what the memory is actually spent on.→
- L4What a model carries between tokensA model has 24 recurrent layers holding 52.69 MB in all, and 8 attention layers. Thirty-two thousand tokens into a conversation, which part holds more memory?Build the memory ledger of two hybrid language models, Mamba-2 and Gated DeltaNet mixers beside attention, from their own configs, and find which part of the state a long conversation is actually paid in.→
AI-Assisted Design
Use the way the industry is actually heading (AI writes the RTL, you verify it) and learn why the verification, not the generation, is the skill.
Economics & Tape-Out
Learn the part no chip course teaches (what it costs to get silicon made, and why open shuttles democratize it) then take your design to a real fab.
- L2The Cost of Getting MadeA chip's photomask set costs well over $1M, amortized across every chip made. Per chip, at 1,000 units versus 10 million units, that mask cost is roughly…Compare the real cost of paths to silicon and see why leading-edge is esoteric while open shuttles put a real chip within reach.→
- L4Tape Out Your TileYour RTL becomes a fabricated tile. What sets the ceiling on what the tile can do?Connect the whole course into the real flow, RTL to a fabricated tile, and see the node ceiling and the path to a chip you can hold.→
Capstone: Design an Edge-AI Tile
Bring the whole course together: design a single edge-AI accelerator tile for a named role so that every requirement, one per module, is satisfied at once.