Silicon for Physical AI
Design the silicon that runs Physical AI — from a single NAND gate to an edge-AI accelerator, then out to a real chip. Logic, synthesis, timing, quantization, AI-assisted design, and the economics of getting made, with TinyTapeout as the real-fab capstone.
▶ Start the course ← All coursesLogic From One Gate
Build every logic function from a single universal gate, then compose those gates into an adder — the ground floor every chip stands on.
- L1The Universal GateBuild AND, OR, and NOT using only NAND — proving one gate is enough to compute anything.→
- L2The AdderCompose gates into a full adder, then chain them into an 8-bit ripple-carry adder that actually adds.→
- L2Write It in VerilogWrite a real adder in Verilog and synthesize it with the actual Yosys — then watch it pass on the synthesized netlist.→
Synthesis & The Cost of Logic
See what a synthesis tool actually does — shrink logic to fewer gates — and why timing (the critical path) decides how fast a chip can run.
- L2Synthesize: Fewer GatesTake a function written as a raw sum of every true row and factor it into far fewer gates — what logic synthesis (Yosys) does for a living.→
- L3The Critical PathCompute a design's critical-path delay and see why a ripple-carry adder can't hit a fast clock — the timing half of PPA.→
The Edge-AI Accelerator
Build the compute at the heart of every AI chip — the multiply-accumulate array — then quantize it to int8, the trick that makes inference fit on a Physical-AI device.
- L3The MAC ArrayBuild a multiply-accumulate array that performs a matrix multiply, and count the MACs — the fundamental work of a neural accelerator.→
- L4Quantize for the EdgeQuantize a float matmul to int8 and show the accuracy holds — the move that lets Physical-AI inference run in a fraction of the power and memory.→
AI-Assisted Design
Use the way the industry is actually heading — AI writes the RTL, you verify it — and learn why the verification, not the generation, is the skill.
Economics & Tape-Out
Learn the part no chip course teaches — what it costs to get silicon made, and why open shuttles democratize it — then take your design to a real fab.
- L2The Cost of Getting MadeCompare the real cost of paths to silicon and see why leading-edge is esoteric while open shuttles put a real chip within reach.→
- L4Tape Out Your TileConnect the whole course into the real flow — RTL to a fabricated tile — and see the honest node ceiling and the path to a chip you can hold.→
Capstone: Design an Edge-AI Tile
Bring the whole course together: design a single edge-AI accelerator tile for a named role so that every requirement, one per module, is satisfied at once.