VERILOG · YOSYS

Write It in Verilog

Write a real adder in Verilog and synthesize it with the actual Yosys — then watch it pass on the synthesized netlist.

01Challenge

You built an adder from gates by hand. Now describe it the way chip designers do — in Verilog — and let the real Yosys synthesizer turn your code into a gate netlist. Complete the 4-bit adder so it passes every test vector.

02Model

Nobody hand-wires millions of gates. Chip designers write Verilog — a hardware description language — and a synthesizer compiles it into gates, exactly as a compiler turns C into machine code. This bench runs the real Yosys (the open-source synthesizer, compiled to WebAssembly): you write a module, it synthesizes to a netlist of cells, and we simulate that netlist against test vectors to grade you. The point is that assign sum = a + b + cin becomes the adder you built by hand last lesson — the tool works out the gates. This is how real RTL design works.

03Guided practice

Worked: read the module ports (a, b, cin, sum). Faded: drive sum with the sum of the inputs plus the carry-in. Independent: synthesize and pass every vector.

04Feedback

PASS WHEN Real Verilog, synthesized by the real Yosys, correct on every vector — you just did RTL design.

If your run fails, check:

Not passing yet — sum should be a + b + cin. In Verilog, assign sum = a + b + cin; lets the 5-bit result hold the carry.
Synthesis failed — check the module is named top and every statement ends with a semicolon.

05Retrieve & space

What does a synthesizer like Yosys do? (Compiles your Verilog into a gate/cell netlist — a compiler for hardware.)
Why is sum 5 bits for a 4-bit add? (To hold the carry-out: 15+15+1 = 31 needs 5 bits.)
What actually ran here? (The real Yosys, compiled to WebAssembly — no cloud.)

06Mastery & project

Writes synthesizable Verilog for an adder and verifies it on the synthesized netlist (L2: real RTL design with an industry synthesizer).

This is the same flow — write RTL, synthesize, verify — that the Module-5 capstone takes all the way to a TinyTapeout chip.

← The Adder Synthesize: Fewer Gates →

VERILOG · YOSYS

Write It in Verilog

Complete the 4-bit adder, then synthesize it with the real Yosys and test it on the netlist.

You read

the module ports and the test vectors that grade you

You change

the Verilog you write inside the module

Fixed

the real Yosys synthesizer and the netlist simulator