Every module was one axis of a single chip. Now you set them all at once. The brief: a wake-word tile for a hearable, the always-on ear that listens for a trigger phrase and wakes the rest of the device. It is the hardest kind of edge silicon, because it never sleeps, so it lives or dies on power and area, and it is only real if it can be fabricated for a price a student or a startup can pay. The axes pull against each other. A bigger MAC array hits the throughput but costs area; a wider accumulator keeps the math correct but costs bits; float weights would be accurate but never fit the on-chip memory, so you quantize; and none of it matters until timing closes and the verification passes and the fab route lands inside the budget. That is chip design: not one clever block, but a whole tile where logic, timing, compute, memory, verification, and economics all hold at once. Set every parameter and make them all pass together.