This is where the course becomes real silicon. The whole flow now runs end to end: write Verilog and synthesize it with Yosys (YoWASP), inspect it as a live circuit in DigitalJS, harden RTL to a GDS layout through the open OpenLane/LibreLane flow on the SKY130 open PDK, and submit a TinyTapeout tile — which rides a shared shuttle to a fab and comes back, weeks later, as a chip you can hold. The node is honest: open PDKs are 130/180nm, plenty for an edge-AI tile and for learning, not the leading edge. That is the point of the Diffusion Layer — access, not the apex — because the chip in your hand is what turns a student into a chip designer.