One digest

One Digest: Bit-Identical Neural Computation Across Heterogeneous Compute Fabrics

Making a transformer forward pass compute the same bits in a browser tab, on Apple silicon, and on an NVIDIA GPU — the mechanisms that break it, the pins that hold it, and the measured price.

David Jean Charlot, PhD

Dean of Physical AI · The Charlot Lab, Institute for Physical AI @ BMI

Correspondence: contact@physicalai-bmi.org · physicalai-bmi.org
Reproduction kit: github.com/dcharlot-physicalai-bmi/ferric · scripts/fabric-ci.sh · applied in Ferralloy (ferralloy.physicalai-bmi.org)

1. Why bits, not tolerances

Numerical work usually accepts small cross-platform differences and validates within a tolerance. Three uses make that insufficient for us. Verification: if a robot policy's behavior is to be checked cryptographically — sign the expected outputs, let the device re-run and byte-compare[7] — then "close" is not checkable; only equality is. Education: a student's browser experiment should be exactly reproducible on the instructor's machine, or the discrepancy itself becomes an ungraded mystery. Heterogeneous scheduling: when every substrate computes the same bits, a scheduler may place work on whatever is free — CPU cores, a GPU, a browser tab — without changing any result. Bit-identity converts placement from a correctness question into a pure performance question, which is precisely what makes dynamic heterogeneous compute trustworthy. It is also, we found, indifferent to load: our cross-substrate gate passed unchanged while the same GPU ran a heavy concurrent decoding workload.

2. Where the bits diverge

We probed with a fixed instrument: deterministic integer-generated inputs (xorshift with mantissa bitcast — no library math anywhere), each kernel's raw output bits hashed with FNV-1a, and, as ground truth, plain-IEEE CPU replicas of every operation sequence in Rust, whose f32 arithmetic is round-to-nearest with no fast-math by construction. Divergences localized to five mechanisms:

(i) Fast-math shader compilation. Metal compiles shaders with fast math unless told otherwise; wgpu never told it otherwise. A barriered Newton–Raphson sequence deviated from the IEEE replica on 183 of 768 inputs (1 ulp) on Metal and on 0 of 768 on NVIDIA Vulkan — the forensic that first separated compiler behavior from hardware behavior. The pin: MTLMathModeSafe.

(ii) fma contraction, three independent levels. SPIR-V permits drivers to fuse a*b+c unless each operation carries a NoContraction decoration; NVIDIA fuses. Metal contracts even under safe math — floating-point contraction is a separate, default-on setting (FP_CONTRACT). And a browser's WGSL compiler (Tint) contracts on its own schedule. Two compilers that both fuse can agree by coincidence; we observed exactly that, and observed the agreement dissolve the moment one side was pinned.

(iii) Register promotion. Source-level barriers (bit-casting through an opaque runtime value) hold only until the compiler promotes the surrounding memory into registers and re-applies (i) and (ii). We measured, in one browser compiler: private arrays promoted whenever indices were provably thread-private; barrier-free workgroup memory promoted in straight-line code but not in dynamic-trip loops; the same function fused in one inlining context and not in another. The behavior is real, reproducible — and unreliable, which for a guarantee is the same as absent.

(iv) Host library math. sinf differs by ulps between macOS and glibc; model weights generated through host libm made "the same model" differ across machines before a single shader ran.

(v) Vendor transcendentals. GPU built-in exp/sin/cos/sqrt — and division — have implementation-defined precision and differ across vendors regardless of every setting above.

3. The pins, in order of strength

Each mechanism has a countermeasure; the campaign's central finding is their strict ordering.

Table 1. The pin hierarchy. Storage memory is host-visible, so no conforming compiler may elide, reorder, fuse, or promote across it — the one pin that held unconditionally, including in the browser.

Parallel reductions fit the same discipline with fixed shapes: 64 strided partial classes and a six-level add tree through barrier-separated phases, with each phase's reader assigned a different thread's stride class than its writer — a rotation that defeats privatization while provably preserving values (the tree pairing commutes with class rotation). Warp-level reduction joins the contract by replacing the driver's subgroupAdd (whose order is its own) with five explicit subgroupShuffleXor pairwise adds and a canonical lane broadcast, the subgroup width and lane mapping declared as part of the algorithm's shape.

4. Results: six substrates, one digest

Table 2. Selected rows of the 17-row probe (23 July 2026). A policy trained in a browser carries a behavioral signature that any Metal or Vulkan device can verify bit-exactly — the digest, not a tolerance, is the contract.

5. Opaque accelerators: the family-oracle contract

Neural engines sit behind compilers that are not ours to pin, so the one-digest contract cannot reach them; pretending otherwise would be the assumption this program exists to eliminate. The honest second tier: measure what a device family produces for a fixed (model, precision, compute-units, inputs) tuple, and pin that as the family's oracle. We established the contract's necessary conditions on Apple's Neural Engine (M5 Max, CoreML):

Table 3. The ANE grid (4×(matmul 1024² + relu) on 256×1024). Engagement is twice-witnessed — 2.3× speedup and a distinct digest. Three deterministic execution families coexist on one chip; each can carry an oracle.

The grid also surfaced the traps a naïve integration ships: fp32 programs silently never reach the ANE (identical digest and time to CPU — one would believe oneself NPU-verified and be wrong); small models never leave the CPU at all; and the ALL scheduler setting picks different units for different programs. Oracle contracts therefore pin explicit compute units and precision, and version their oracle store by (family, OS, compiler) until cross-device and cross-update stability are measured — which requires hardware we do not yet have, and is stated as such.

6. The measured price

Table 4. Idle-machine, batched-dispatch, minimum of five runs per generation (Metal, M5 Max). Full cross-substrate determinism costs +15–53% per kernel against the pre-campaign fast path.

Two methodological corrections stand in the record. Early per-op measurements included an 8 MB readback and overstated the cost by up to 6× — those numbers measured the bus. And our prediction that the parallel tree kernels would beat the fast baseline was wrong: on an idle GPU at these shapes, one-thread-per-row already saturates the machine, sequential deterministic kernels edge the trees for two of three norms, and only LayerNorm's tree wins decisively. Tree-versus-sequential is shape-dependent; both remain available under the same digest contract, so the choice is purely a performance one.

7. What this enables, and what it does not

The two-tier contract is now load-bearing in an open toolchain: signed policy packs whose eval vectors are recorded on one substrate and verified bit-exactly on another before an update goes live[7]; classroom experiments whose browser results match the reference machine to the bit; and free placement of deterministic kernels across any pinned substrate. It does not give cross-family identity for opaque accelerators (by design), does not yet cover tensor-unit matrix paths (their accumulation order is not pinnable today; they stay off the contract until it is), and depends on compilers we do not control continuing to respect storage semantics — which conformance requires, and which the one-command gate re-verifies on every run rather than assumes. Everything here — kernels, forks, probes, forensic method, and this report — is published under MIT/Apache for anyone to use, check, teach from, or improve.

References

1. W3C. WebGPU Shading Language (WGSL), W3C Working Draft, 2026 — floating-point accuracy and subgroup built-ins.
2. Khronos Group. SPIR-V Specification — the NoContraction decoration and permitted operation contraction.
3. Apple. Metal Shading Language Specification — math modes and floating-point contraction semantics.
4. D. Goldberg. "What Every Computer Scientist Should Know About Floating-Point Arithmetic." ACM Computing Surveys 23(1), 1991.
5. IEEE. IEEE 754-2019 Standard for Floating-Point Arithmetic.
6. gfx-rs contributors. wgpu and naga — the portable GPU stack this work builds on, maintained here as patchable forks.
7. Institute for Physical AI @ BMI. Ferralloy: signed, verified-behavior packs for physical-AI fleets. ferralloy.physicalai-bmi.org, 2026.
8. Apple. Core ML Tools (coremltools 9) — MIL programs and compute-unit selection.
9. Institute for Physical AI @ BMI. Cross-fabric determinism: campaign log and forensic method. github.com/dcharlot-physicalai-bmi/ferric, docs/determinism/, 2026.